1. Field of the Invention
The present invention generally relates to semiconductor fabrication, and particularly to a method for fabrication a semiconductor device.
2. Description of Related Art
As the request to reduce the size of electronic device and increase the operation speed of electronic device, the size of the semiconductor device such as field effect transistor (FET) needs to be accordingly reduced. When size of the FET is greatly reduced, the conventional FET with polysilicon gate cannot be adapted well. So, the structure of FET in 2D structure is no longer suitable for use.
In the technologies under development, a type of fin FET has been proposed. The fin FET is in 3D structure, in which the source/drain region has been raised up from the substrate, like a fin in structure. The gate can be formed as a gate line, crossing over the fin to serve as the gate structure for each FET and also the connection part between the related FET.
The fins for the Fin FETs are formed on the top portion of a semiconductor substrate, such as the silicon substrate. In the beginning the fins are evenly formed on the substrate with equal condition, such as same width of fin. However, depending on the circuit design, the device density or device loading at some area is lower than the other area, becoming rather isolated fin(s). When an oxide layer is forming over the fins, including the isolated fin, by flowable chemical vapor deposition (FCVD) with annealing, the isolated fin in silicon material would be oxidized at the surface more than the usual fins with higher device loading.
As a result, the fin width for the rather isolated fin would be smaller at the end. This phenomenon would affect the performance of the isolated fin FET. This issue in reducing the fin width in fabrication needs to be really concerned.